Module core::arch::arm[−][src]

🔬 This is a nightly-only experimental API. (stdsimd #27731)

This is supported on ARM only.

Platform-specific intrinsics for the arm platform.

See the module documentation for more details.

Structs

APSR	Experimental Application Program Status Register
ISH	Experimental Inner Shareable is the required shareability domain, reads and writes are the required access types
ISHST	Experimental Inner Shareable is the required shareability domain, writes are the required access type
NSH	Experimental Non-shareable is the required shareability domain, reads and writes are the required access types
NSHST	Experimental Non-shareable is the required shareability domain, writes are the required access type
OSH	Experimental Outer Shareable is the required shareability domain, reads and writes are the required access types
OSHST	Experimental Outer Shareable is the required shareability domain, writes are the required access type
ST	Experimental Full system is the required shareability domain, writes are the required access type
SY	Experimental Full system is the required shareability domain, reads and writes are the required access types
float32x2_t	Experimental ARM-specific 64-bit wide vector of two packed `f32`.
float32x4_t	Experimental ARM-specific 128-bit wide vector of four packed `f32`.
int8x4_t	Experimental ARM-specific 32-bit wide vector of four packed `i8`.
int8x8_t	Experimental ARM-specific 64-bit wide vector of eight packed `i8`.
int8x8x2_t	Experimental ARM-specific type containing two `int8x8_t` vectors.
int8x8x3_t	Experimental ARM-specific type containing three `int8x8_t` vectors.
int8x8x4_t	Experimental ARM-specific type containing four `int8x8_t` vectors.
int8x16_t	Experimental ARM-specific 128-bit wide vector of sixteen packed `i8`.
int16x2_t	Experimental ARM-specific 32-bit wide vector of two packed `i16`.
int16x4_t	Experimental ARM-specific 64-bit wide vector of four packed `i16`.
int16x8_t	Experimental ARM-specific 128-bit wide vector of eight packed `i16`.
int32x2_t	Experimental ARM-specific 64-bit wide vector of two packed `i32`.
int32x4_t	Experimental ARM-specific 128-bit wide vector of four packed `i32`.
int64x1_t	Experimental ARM-specific 64-bit wide vector of one packed `i64`.
int64x2_t	Experimental ARM-specific 128-bit wide vector of two packed `i64`.
poly8x8_t	Experimental ARM-specific 64-bit wide polynomial vector of eight packed `p8`.
poly8x8x2_t	Experimental ARM-specific type containing two `poly8x8_t` vectors.
poly8x8x3_t	Experimental ARM-specific type containing three `poly8x8_t` vectors.
poly8x8x4_t	Experimental ARM-specific type containing four `poly8x8_t` vectors.
poly8x16_t	Experimental ARM-specific 128-bit wide vector of sixteen packed `p8`.
poly16x4_t	Experimental ARM-specific 64-bit wide vector of four packed `p16`.
poly16x8_t	Experimental ARM-specific 128-bit wide vector of eight packed `p16`.
poly64x1_t	Experimental ARM-specific 64-bit wide vector of one packed `p64`.
poly64x2_t	Experimental ARM-specific 128-bit wide vector of two packed `p64`.
uint8x4_t	Experimental ARM-specific 32-bit wide vector of four packed `u8`.
uint8x8_t	Experimental ARM-specific 64-bit wide vector of eight packed `u8`.
uint8x8x2_t	Experimental ARM-specific type containing two `uint8x8_t` vectors.
uint8x8x3_t	Experimental ARM-specific type containing three `uint8x8_t` vectors.
uint8x8x4_t	Experimental ARM-specific type containing four `uint8x8_t` vectors.
uint8x16_t	Experimental ARM-specific 128-bit wide vector of sixteen packed `u8`.
uint16x2_t	Experimental ARM-specific 32-bit wide vector of two packed `u16`.
uint16x4_t	Experimental ARM-specific 64-bit wide vector of four packed `u16`.
uint16x8_t	Experimental ARM-specific 128-bit wide vector of eight packed `u16`.
uint32x2_t	Experimental ARM-specific 64-bit wide vector of two packed `u32`.
uint32x4_t	Experimental ARM-specific 128-bit wide vector of four packed `u32`.
uint64x1_t	Experimental ARM-specific 64-bit wide vector of one packed `u64`.
uint64x2_t	Experimental ARM-specific 128-bit wide vector of two packed `u64`.

Functions

__breakpoint ^⚠	Experimental Inserts a breakpoint instruction.
__clrex ^⚠	Experimental Removes the exclusive lock created by LDREX
__crc32b ^⚠	Experimental`crc` and `v8` CRC32 single round checksum for bytes (8 bits).
__crc32cb ^⚠	Experimental`crc` and `v8` CRC32-C single round checksum for bytes (8 bits).
__crc32ch ^⚠	Experimental`crc` and `v8` CRC32-C single round checksum for half words (16 bits).
__crc32cw ^⚠	Experimental`crc` and `v8` CRC32-C single round checksum for words (32 bits).
__crc32h ^⚠	Experimental`crc` and `v8` CRC32 single round checksum for half words (16 bits).
__crc32w ^⚠	Experimental`crc` and `v8` CRC32 single round checksum for words (32 bits).
__dbg ^⚠	Experimental Generates a DBG instruction.
__dmb ^⚠	Experimental Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction.
__dsb ^⚠	Experimental Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction.
__isb ^⚠	Experimental Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction.
__ldrex ^⚠	Experimental Executes a exclusive LDR instruction for 32 bit value.
__ldrexb ^⚠	Experimental Executes a exclusive LDR instruction for 8 bit value.
__ldrexh ^⚠	Experimental Executes a exclusive LDR instruction for 16 bit value.
__nop ^⚠	Experimental Generates an unspecified no-op instruction.
__qadd ^⚠	Experimental Signed saturating addition
__qadd8 ^⚠	Experimental Saturating four 8-bit integer additions
__qadd16 ^⚠	Experimental Saturating two 16-bit integer additions
__qasx ^⚠	Experimental Returns the 16-bit signed saturated equivalent of
__qdbl ^⚠	Experimental Insert a QADD instruction
__qsax ^⚠	Experimental Returns the 16-bit signed saturated equivalent of
__qsub ^⚠	Experimental Signed saturating subtraction
__qsub8 ^⚠	Experimental Saturating two 8-bit integer subtraction
__qsub16 ^⚠	Experimental Saturating two 16-bit integer subtraction
__rsr ^⚠	Experimental Reads a 32-bit system register
__rsrp ^⚠	Experimental Reads a system register containing an address
__sadd8 ^⚠	Experimental Returns the 8-bit signed saturated equivalent of
__sadd16 ^⚠	Experimental Returns the 16-bit signed saturated equivalent of
__sasx ^⚠	Experimental Returns the 16-bit signed equivalent of
__sel ^⚠	Experimental Select bytes from each operand according to APSR GE flags
__sev ^⚠	Experimental Generates a SEV (send a global event) hint instruction.
__shadd8 ^⚠	Experimental Signed halving parallel byte-wise addition.
__shadd16 ^⚠	Experimental Signed halving parallel halfword-wise addition.
__shsub8 ^⚠	Experimental Signed halving parallel byte-wise subtraction.
__shsub16 ^⚠	Experimental Signed halving parallel halfword-wise subtraction.
__smlabb ^⚠	Experimental Insert a SMLABB instruction
__smlabt ^⚠	Experimental Insert a SMLABT instruction
__smlad ^⚠	Experimental Dual 16-bit Signed Multiply with Addition of products and 32-bit accumulation.
__smlatb ^⚠	Experimental Insert a SMLATB instruction
__smlatt ^⚠	Experimental Insert a SMLATT instruction
__smlawb ^⚠	Experimental Insert a SMLAWB instruction
__smlawt ^⚠	Experimental Insert a SMLAWT instruction
__smlsd ^⚠	Experimental Dual 16-bit Signed Multiply with Subtraction of products and 32-bit accumulation and overflow detection.
__smuad ^⚠	Experimental Signed Dual Multiply Add.
__smuadx ^⚠	Experimental Signed Dual Multiply Add Reversed.
__smulbb ^⚠	Experimental Insert a SMULBB instruction
__smulbt ^⚠	Experimental Insert a SMULTB instruction
__smultb ^⚠	Experimental Insert a SMULTB instruction
__smultt ^⚠	Experimental Insert a SMULTT instruction
__smulwb ^⚠	Experimental Insert a SMULWB instruction
__smulwt ^⚠	Experimental Insert a SMULWT instruction
__smusd ^⚠	Experimental Signed Dual Multiply Subtract.
__smusdx ^⚠	Experimental Signed Dual Multiply Subtract Reversed.
__ssub8 ^⚠	Experimental Inserts a `SSUB8` instruction.
__strex ^⚠	Experimental Executes a exclusive STR instruction for 32 bit values
__strexb ^⚠	Experimental Executes a exclusive STR instruction for 8 bit values
__strexh ^⚠	Experimental Executes a exclusive STR instruction for 16 bit values
__usad8 ^⚠	Experimental Sum of 8-bit absolute differences.
__usada8 ^⚠	Experimental Sum of 8-bit absolute differences and constant.
__usub8 ^⚠	Experimental Inserts a `USUB8` instruction.
__wfe ^⚠	Experimental Generates a WFE (wait for event) hint instruction, or nothing.
__wfi ^⚠	Experimental Generates a WFI (wait for interrupt) hint instruction, or nothing.
__wsr ^⚠	Experimental Writes a 32-bit system register
__wsrp ^⚠	Experimental Writes a system register containing an address
__yield ^⚠	Experimental Generates a YIELD hint instruction.
_clz_u8 ^⚠	Experimental`v7` Count Leading Zeros.
_clz_u16 ^⚠	Experimental`v7` Count Leading Zeros.
_clz_u32 ^⚠	Experimental`v7` Count Leading Zeros.
_rbit_u32 ^⚠	Experimental`v7` Reverse the bit order.
_rev_u16 ^⚠	Experimental Reverse the order of the bytes.
_rev_u32 ^⚠	Experimental Reverse the order of the bytes.
udf ^⚠	Experimental Generates the trap instruction `UDF`
vabs_s8 ^⚠	Experimental`neon` and `v7` Absolute value (wrapping).
vabs_s16 ^⚠	Experimental`neon` and `v7` Absolute value (wrapping).
vabs_s32 ^⚠	Experimental`neon` and `v7` Absolute value (wrapping).
vabsq_s8 ^⚠	Experimental`neon` and `v7` Absolute value (wrapping).
vabsq_s16 ^⚠	Experimental`neon` and `v7` Absolute value (wrapping).
vabsq_s32 ^⚠	Experimental`neon` and `v7` Absolute value (wrapping).
vadd_f32 ^⚠	Experimental`neon` and `v7` Vector add.
vadd_s8 ^⚠	Experimental`neon` and `v7` Vector add.
vadd_s16 ^⚠	Experimental`neon` and `v7` Vector add.
vadd_s32 ^⚠	Experimental`neon` and `v7` Vector add.
vadd_u8 ^⚠	Experimental`neon` and `v7` Vector add.
vadd_u16 ^⚠	Experimental`neon` and `v7` Vector add.
vadd_u32 ^⚠	Experimental`neon` and `v7` Vector add.
vaddhn_high_s16 ^⚠	Experimental`neon` and `v7` Add returning High Narrow (high half).
vaddhn_high_s32 ^⚠	Experimental`neon` and `v7` Add returning High Narrow (high half).
vaddhn_high_s64 ^⚠	Experimental`neon` and `v7` Add returning High Narrow (high half).
vaddhn_high_u16 ^⚠	Experimental`neon` and `v7` Add returning High Narrow (high half).
vaddhn_high_u32 ^⚠	Experimental`neon` and `v7` Add returning High Narrow (high half).
vaddhn_high_u64 ^⚠	Experimental`neon` and `v7` Add returning High Narrow (high half).
vaddhn_s16 ^⚠	Experimental`neon` and `v7` Add returning High Narrow.
vaddhn_s32 ^⚠	Experimental`neon` and `v7` Add returning High Narrow.
vaddhn_s64 ^⚠	Experimental`neon` and `v7` Add returning High Narrow.
vaddhn_u16 ^⚠	Experimental`neon` and `v7` Add returning High Narrow.
vaddhn_u32 ^⚠	Experimental`neon` and `v7` Add returning High Narrow.
vaddhn_u64 ^⚠	Experimental`neon` and `v7` Add returning High Narrow.
vaddl_high_s8 ^⚠	Experimental`neon` and `v7` Signed Add Long (vector, high half).
vaddl_high_s16 ^⚠	Experimental`neon` and `v7` Signed Add Long (vector, high half).
vaddl_high_s32 ^⚠	Experimental`neon` and `v7` Signed Add Long (vector, high half).
vaddl_high_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add Long (vector, high half).
vaddl_high_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add Long (vector, high half).
vaddl_high_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add Long (vector, high half).
vaddl_s8 ^⚠	Experimental`neon` and `v7` Signed Add Long (vector).
vaddl_s16 ^⚠	Experimental`neon` and `v7` Signed Add Long (vector).
vaddl_s32 ^⚠	Experimental`neon` and `v7` Signed Add Long (vector).
vaddl_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add Long (vector).
vaddl_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add Long (vector).
vaddl_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add Long (vector).
vaddq_f32 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_s8 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_s16 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_s32 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_s64 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_u8 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_u16 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_u32 ^⚠	Experimental`neon` and `v7` Vector add.
vaddq_u64 ^⚠	Experimental`neon` and `v7` Vector add.
vaddw_high_s8 ^⚠	Experimental`neon` and `v7` Signed Add Wide (high half).
vaddw_high_s16 ^⚠	Experimental`neon` and `v7` Signed Add Wide (high half).
vaddw_high_s32 ^⚠	Experimental`neon` and `v7` Signed Add Wide (high half).
vaddw_high_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add Wide (high half).
vaddw_high_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add Wide (high half).
vaddw_high_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add Wide (high half).
vaddw_s8 ^⚠	Experimental`neon` and `v7` Signed Add Wide.
vaddw_s16 ^⚠	Experimental`neon` and `v7` Signed Add Wide.
vaddw_s32 ^⚠	Experimental`neon` and `v7` Signed Add Wide.
vaddw_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add Wide.
vaddw_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add Wide.
vaddw_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add Wide.
vaesdq_u8 ^⚠	Experimental`crypto` and `v8` AES single round decryption.
vaeseq_u8 ^⚠	Experimental`crypto` and `v8` AES single round encryption.
vaesimcq_u8 ^⚠	Experimental`crypto` and `v8` AES inverse mix columns.
vaesmcq_u8 ^⚠	Experimental`crypto` and `v8` AES mix columns.
vand_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_s64 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vand_u64 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_s64 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vandq_u64 ^⚠	Experimental`neon` and `v7` Vector bitwise and
vceq_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare equal
vceq_s8 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceq_s16 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceq_s32 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceq_u8 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceq_u16 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceq_u32 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceqq_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare equal
vceqq_s8 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceqq_s16 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceqq_s32 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceqq_u8 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceqq_u16 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vceqq_u32 ^⚠	Experimental`neon` and `v7` Compare bitwise Equal (vector)
vcge_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare greater than or equal
vcge_s8 ^⚠	Experimental`neon` and `v7` Compare signed greater than or equal
vcge_s16 ^⚠	Experimental`neon` and `v7` Compare signed greater than or equal
vcge_s32 ^⚠	Experimental`neon` and `v7` Compare signed greater than or equal
vcge_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned greater than or equal
vcge_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned greater than or equal
vcge_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned greater than or equal
vcgeq_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare greater than or equal
vcgeq_s8 ^⚠	Experimental`neon` and `v7` Compare signed greater than or equal
vcgeq_s16 ^⚠	Experimental`neon` and `v7` Compare signed greater than or equal
vcgeq_s32 ^⚠	Experimental`neon` and `v7` Compare signed greater than or equal
vcgeq_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned greater than or equal
vcgeq_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned greater than or equal
vcgeq_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned greater than or equal
vcgt_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare greater than
vcgt_s8 ^⚠	Experimental`neon` and `v7` Compare signed greater than
vcgt_s16 ^⚠	Experimental`neon` and `v7` Compare signed greater than
vcgt_s32 ^⚠	Experimental`neon` and `v7` Compare signed greater than
vcgt_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned highe
vcgt_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned highe
vcgt_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned highe
vcgtq_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare greater than
vcgtq_s8 ^⚠	Experimental`neon` and `v7` Compare signed greater than
vcgtq_s16 ^⚠	Experimental`neon` and `v7` Compare signed greater than
vcgtq_s32 ^⚠	Experimental`neon` and `v7` Compare signed greater than
vcgtq_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned highe
vcgtq_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned highe
vcgtq_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned highe
vcle_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare less than or equal
vcle_s8 ^⚠	Experimental`neon` and `v7` Compare signed less than or equal
vcle_s16 ^⚠	Experimental`neon` and `v7` Compare signed less than or equal
vcle_s32 ^⚠	Experimental`neon` and `v7` Compare signed less than or equal
vcle_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned less than or equal
vcle_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned less than or equal
vcle_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned less than or equal
vcleq_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare less than or equal
vcleq_s8 ^⚠	Experimental`neon` and `v7` Compare signed less than or equal
vcleq_s16 ^⚠	Experimental`neon` and `v7` Compare signed less than or equal
vcleq_s32 ^⚠	Experimental`neon` and `v7` Compare signed less than or equal
vcleq_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned less than or equal
vcleq_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned less than or equal
vcleq_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned less than or equal
vclt_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare less than
vclt_s8 ^⚠	Experimental`neon` and `v7` Compare signed less than
vclt_s16 ^⚠	Experimental`neon` and `v7` Compare signed less than
vclt_s32 ^⚠	Experimental`neon` and `v7` Compare signed less than
vclt_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned less than
vclt_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned less than
vclt_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned less than
vcltq_f32 ^⚠	Experimental`neon` and `v7` Floating-point compare less than
vcltq_s8 ^⚠	Experimental`neon` and `v7` Compare signed less than
vcltq_s16 ^⚠	Experimental`neon` and `v7` Compare signed less than
vcltq_s32 ^⚠	Experimental`neon` and `v7` Compare signed less than
vcltq_u8 ^⚠	Experimental`neon` and `v7` Compare unsigned less than
vcltq_u16 ^⚠	Experimental`neon` and `v7` Compare unsigned less than
vcltq_u32 ^⚠	Experimental`neon` and `v7` Compare unsigned less than
vcnt_p8 ^⚠	Experimental`neon` and `v7` Population count per byte.
vcnt_s8 ^⚠	Experimental`neon` and `v7` Population count per byte.
vcnt_u8 ^⚠	Experimental`neon` and `v7` Population count per byte.
vcntq_p8 ^⚠	Experimental`neon` and `v7` Population count per byte.
vcntq_s8 ^⚠	Experimental`neon` and `v7` Population count per byte.
vcntq_u8 ^⚠	Experimental`neon` and `v7` Population count per byte.
vcvtq_s32_f32 ^⚠	Experimental`neon` and `v7` Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)
vcvtq_u32_f32 ^⚠	Experimental`neon` and `v7` Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)
vdupq_n_s8 ^⚠	Experimental`neon` and `v7` Duplicate vector element to vector or scalar
vdupq_n_u8 ^⚠	Experimental`neon` and `v7` Duplicate vector element to vector or scalar
veor_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_s64 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veor_u64 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_s64 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
veorq_u64 ^⚠	Experimental`neon` and `v7` Vector bitwise exclusive or (vector)
vextq_s8 ^⚠	Experimental`neon` and `v7` Extract vector from pair of vectors
vextq_u8 ^⚠	Experimental`neon` and `v7` Extract vector from pair of vectors
vget_lane_u8 ^⚠	Experimental`neon` and `v7` Move vector element to general-purpose register
vget_lane_u64 ^⚠	Experimental`neon` and `v7` Move vector element to general-purpose register
vgetq_lane_s32 ^⚠	Experimental`neon` and `v7` Move vector element to general-purpose register
vgetq_lane_u16 ^⚠	Experimental`neon` and `v7` Move vector element to general-purpose register
vgetq_lane_u32 ^⚠	Experimental`neon` and `v7` Move vector element to general-purpose register
vgetq_lane_u64 ^⚠	Experimental`neon` and `v7` Move vector element to general-purpose register
vhadd_s8 ^⚠	Experimental`neon` and `v7` Halving add
vhadd_s16 ^⚠	Experimental`neon` and `v7` Halving add
vhadd_s32 ^⚠	Experimental`neon` and `v7` Halving add
vhadd_u8 ^⚠	Experimental`neon` and `v7` Halving add
vhadd_u16 ^⚠	Experimental`neon` and `v7` Halving add
vhadd_u32 ^⚠	Experimental`neon` and `v7` Halving add
vhaddq_s8 ^⚠	Experimental`neon` and `v7` Halving add
vhaddq_s16 ^⚠	Experimental`neon` and `v7` Halving add
vhaddq_s32 ^⚠	Experimental`neon` and `v7` Halving add
vhaddq_u8 ^⚠	Experimental`neon` and `v7` Halving add
vhaddq_u16 ^⚠	Experimental`neon` and `v7` Halving add
vhaddq_u32 ^⚠	Experimental`neon` and `v7` Halving add
vhsub_s8 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsub_s16 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsub_s32 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsub_u8 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsub_u16 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsub_u32 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsubq_s8 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsubq_s16 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsubq_s32 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsubq_u8 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsubq_u16 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vhsubq_u32 ^⚠	Experimental`neon` and `v7` Signed halving subtract
vld1_dup_f32 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p8 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_p16 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s8 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s16 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s32 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_s64 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u8 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u16 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u32 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_dup_u64 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1_f32 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_lane_f32 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_p8 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_p16 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_s8 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_s16 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_s32 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_s64 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_u8 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_u16 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_u32 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_lane_u64 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1_p8 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_p16 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_s8 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_s16 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_s32 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_s64 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_u8 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_u16 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_u32 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1_u64 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_dup_f32 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p8 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_p16 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s8 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s16 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s32 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_s64 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u8 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u16 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u32 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_dup_u64 ^⚠	Experimental`neon` and `v7` Load one single-element structure and Replicate to all lanes (of one register).
vld1q_f32 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_lane_f32 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_p8 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_p16 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_s8 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_s16 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_s32 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_s64 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_u8 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_u16 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_u32 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_lane_u64 ^⚠	Experimental`neon` and `v7` Load one single-element structure to one lane of one register.
vld1q_p8 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_p16 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_s8 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_s16 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_s32 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_s64 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_u8 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_u16 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_u32 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vld1q_u64 ^⚠	Experimental`neon,v7` Load multiple single-element structures to one, two, three, or four registers.
vmax_f32 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmax_s8 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmax_s16 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmax_s32 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmax_u8 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmax_u16 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmax_u32 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_f32 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_s8 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_s16 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_s32 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_u8 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_u16 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmaxq_u32 ^⚠	Experimental`neon` and `v7` Maximum (vector)
vmin_f32 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmin_s8 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmin_s16 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmin_s32 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmin_u8 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmin_u16 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmin_u32 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_f32 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_s8 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_s16 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_s32 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_u8 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_u16 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vminq_u32 ^⚠	Experimental`neon` and `v7` Minimum (vector)
vmovl_s8 ^⚠	Experimental`neon` and `v7` Vector long move.
vmovl_s16 ^⚠	Experimental`neon` and `v7` Vector long move.
vmovl_s32 ^⚠	Experimental`neon` and `v7` Vector long move.
vmovl_u8 ^⚠	Experimental`neon` and `v7` Vector long move.
vmovl_u16 ^⚠	Experimental`neon` and `v7` Vector long move.
vmovl_u32 ^⚠	Experimental`neon` and `v7` Vector long move.
vmovn_s16 ^⚠	Experimental`neon` and `v7` Vector narrow integer.
vmovn_s32 ^⚠	Experimental`neon` and `v7` Vector narrow integer.
vmovn_s64 ^⚠	Experimental`neon` and `v7` Vector narrow integer.
vmovn_u16 ^⚠	Experimental`neon` and `v7` Vector narrow integer.
vmovn_u32 ^⚠	Experimental`neon` and `v7` Vector narrow integer.
vmovn_u64 ^⚠	Experimental`neon` and `v7` Vector narrow integer.
vmovq_n_u8 ^⚠	Experimental`neon` and `v7` Duplicate vector element to vector or scalar
vmul_f32 ^⚠	Experimental`neon` and `v7` Multiply
vmul_s8 ^⚠	Experimental`neon` and `v7` Multiply
vmul_s16 ^⚠	Experimental`neon` and `v7` Multiply
vmul_s32 ^⚠	Experimental`neon` and `v7` Multiply
vmul_u8 ^⚠	Experimental`neon` and `v7` Multiply
vmul_u16 ^⚠	Experimental`neon` and `v7` Multiply
vmul_u32 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_f32 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_s8 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_s16 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_s32 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_u8 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_u16 ^⚠	Experimental`neon` and `v7` Multiply
vmulq_u32 ^⚠	Experimental`neon` and `v7` Multiply
vmvn_p8 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvn_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvn_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvn_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvn_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvn_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvn_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_p8 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vmvnq_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise not.
vorr_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_s64 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorr_u64 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_s8 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_s16 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_s32 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_s64 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_u8 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_u16 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_u32 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vorrq_u64 ^⚠	Experimental`neon` and `v7` Vector bitwise or (immediate, inclusive)
vpadal_s8 ^⚠	Experimental`neon` and `v7` Signed Add and Accumulate Long Pairwise.
vpadal_s16 ^⚠	Experimental`neon` and `v7` Signed Add and Accumulate Long Pairwise.
vpadal_s32 ^⚠	Experimental`neon` and `v7` Signed Add and Accumulate Long Pairwise.
vpadal_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add and Accumulate Long Pairwise.
vpadal_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add and Accumulate Long Pairwise.
vpadal_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add and Accumulate Long Pairwise.
vpadalq_s8 ^⚠	Experimental`neon` and `v7` Signed Add and Accumulate Long Pairwise.
vpadalq_s16 ^⚠	Experimental`neon` and `v7` Signed Add and Accumulate Long Pairwise.
vpadalq_s32 ^⚠	Experimental`neon` and `v7` Signed Add and Accumulate Long Pairwise.
vpadalq_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add and Accumulate Long Pairwise.
vpadalq_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add and Accumulate Long Pairwise.
vpadalq_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add and Accumulate Long Pairwise.
vpadd_s8 ^⚠	Experimental`neon` and `v7` Add pairwise.
vpadd_s16 ^⚠	Experimental`neon` and `v7` Add pairwise.
vpadd_s32 ^⚠	Experimental`neon` and `v7` Add pairwise.
vpadd_u8 ^⚠	Experimental`neon` and `v7` Add pairwise.
vpadd_u16 ^⚠	Experimental`neon` and `v7` Add pairwise.
vpadd_u32 ^⚠	Experimental`neon` and `v7` Add pairwise.
vpaddl_s8 ^⚠	Experimental`neon` and `v7` Signed Add Long Pairwise.
vpaddl_s16 ^⚠	Experimental`neon` and `v7` Signed Add Long Pairwise.
vpaddl_s32 ^⚠	Experimental`neon` and `v7` Signed Add Long Pairwise.
vpaddl_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add Long Pairwise.
vpaddl_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add Long Pairwise.
vpaddl_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add Long Pairwise.
vpaddlq_s8 ^⚠	Experimental`neon` and `v7` Signed Add Long Pairwise.
vpaddlq_s16 ^⚠	Experimental`neon` and `v7` Signed Add Long Pairwise.
vpaddlq_s32 ^⚠	Experimental`neon` and `v7` Signed Add Long Pairwise.
vpaddlq_u8 ^⚠	Experimental`neon` and `v7` Unsigned Add Long Pairwise.
vpaddlq_u16 ^⚠	Experimental`neon` and `v7` Unsigned Add Long Pairwise.
vpaddlq_u32 ^⚠	Experimental`neon` and `v7` Unsigned Add Long Pairwise.
vpmax_f32 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmax_s8 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmax_s16 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmax_s32 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmax_u8 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmax_u16 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmax_u32 ^⚠	Experimental`neon` and `v7` Folding maximum of adjacent pairs
vpmin_f32 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vpmin_s8 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vpmin_s16 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vpmin_s32 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vpmin_u8 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vpmin_u16 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vpmin_u32 ^⚠	Experimental`neon` and `v7` Folding minimum of adjacent pairs
vqadd_s8 ^⚠	Experimental`neon` and `v7` Saturating add
vqadd_s16 ^⚠	Experimental`neon` and `v7` Saturating add
vqadd_s32 ^⚠	Experimental`neon` and `v7` Saturating add
vqadd_u8 ^⚠	Experimental`neon` and `v7` Saturating add
vqadd_u16 ^⚠	Experimental`neon` and `v7` Saturating add
vqadd_u32 ^⚠	Experimental`neon` and `v7` Saturating add
vqaddq_s8 ^⚠	Experimental`neon` and `v7` Saturating add
vqaddq_s16 ^⚠	Experimental`neon` and `v7` Saturating add
vqaddq_s32 ^⚠	Experimental`neon` and `v7` Saturating add
vqaddq_u8 ^⚠	Experimental`neon` and `v7` Saturating add
vqaddq_u16 ^⚠	Experimental`neon` and `v7` Saturating add
vqaddq_u32 ^⚠	Experimental`neon` and `v7` Saturating add
vqmovn_u64 ^⚠	Experimental`neon` and `v7` Unsigned saturating extract narrow.
vqsub_s8 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsub_s16 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsub_s32 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsub_u8 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsub_u16 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsub_u32 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsubq_s8 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsubq_s16 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsubq_s32 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsubq_u8 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsubq_u16 ^⚠	Experimental`neon` and `v7` Saturating subtract
vqsubq_u32 ^⚠	Experimental`neon` and `v7` Saturating subtract
vraddhn_high_s16 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow (high half).
vraddhn_high_s32 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow (high half).
vraddhn_high_s64 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow (high half).
vraddhn_high_u16 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow (high half).
vraddhn_high_u32 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow (high half).
vraddhn_high_u64 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow (high half).
vraddhn_s16 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow.
vraddhn_s32 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow.
vraddhn_s64 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow.
vraddhn_u16 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow.
vraddhn_u32 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow.
vraddhn_u64 ^⚠	Experimental`neon` and `v7` Rounding Add returning High Narrow.
vreinterpret_u64_u32 ^⚠	Experimental`neon` and `v7` Vector reinterpret cast operation
vreinterpretq_s8_u8 ^⚠	Experimental`neon` and `v7` Vector reinterpret cast operation
vreinterpretq_u8_s8 ^⚠	Experimental`neon` and `v7` Vector reinterpret cast operation
vreinterpretq_u16_u8 ^⚠	Experimental`neon` and `v7` Vector reinterpret cast operation
vreinterpretq_u32_u8 ^⚠	Experimental`neon` and `v7` Vector reinterpret cast operation
vreinterpretq_u64_u8 ^⚠	Experimental`neon` and `v7` Vector reinterpret cast operation
vrev16_p8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev16_s8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev16_u8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev16q_p8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev16q_s8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev16q_u8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32_p8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32_s8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32_u8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32_u16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32q_p8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32q_s8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32q_u8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev32q_u16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_f32 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_p8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_p16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_s8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_s16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_s32 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_u8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_u16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64_u32 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_f32 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_p8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_p16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_s8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_s16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_s32 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_u8 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_u16 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrev64q_u32 ^⚠	Experimental`neon` and `v7` Reversing vector elements (swap endianness)
vrhadd_s8 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhadd_s16 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhadd_s32 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhadd_u8 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhadd_u16 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhadd_u32 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhaddq_s8 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhaddq_s16 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhaddq_s32 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhaddq_u8 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhaddq_u16 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrhaddq_u32 ^⚠	Experimental`neon` and `v7` Rounding halving add
vrsqrte_f32 ^⚠	Experimental`neon` Reciprocal square-root estimate.
vsha1cq_u32 ^⚠	Experimental`crypto` and `v8` SHA1 hash update accelerator, choose.
vsha1h_u32 ^⚠	Experimental`crypto` and `v8` SHA1 fixed rotate.
vsha1mq_u32 ^⚠	Experimental`crypto` and `v8` SHA1 hash update accelerator, majority.
vsha1pq_u32 ^⚠	Experimental`crypto` and `v8` SHA1 hash update accelerator, parity.
vsha1su0q_u32 ^⚠	Experimental`crypto` and `v8` SHA1 schedule update accelerator, first part.
vsha1su1q_u32 ^⚠	Experimental`crypto` and `v8` SHA1 schedule update accelerator, second part.
vsha256h2q_u32 ^⚠	Experimental`crypto` and `v8` SHA256 hash update accelerator, upper part.
vsha256hq_u32 ^⚠	Experimental`crypto` and `v8` SHA256 hash update accelerator.
vsha256su0q_u32 ^⚠	Experimental`crypto` and `v8` SHA256 schedule update accelerator, first part.
vsha256su1q_u32 ^⚠	Experimental`crypto` and `v8` SHA256 schedule update accelerator, second part.
vshlq_n_u8 ^⚠	Experimental`neon` and `v7` Shift right
vshrq_n_u8 ^⚠	Experimental`neon` and `v7` Unsigned shift right
vsli_n_p8 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_p16 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_s8 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_s16 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_s32 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_s64 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_u8 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_u16 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_u32 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsli_n_u64 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_p8 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_p16 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_s8 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_s16 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_s32 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_s64 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_u8 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_u16 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_u32 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsliq_n_u64 ^⚠	Experimental`neon,v7` Shift Left and Insert (immediate)
vsri_n_p8 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_p16 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_s8 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_s16 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_s32 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_s64 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_u8 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_u16 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_u32 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsri_n_u64 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_p8 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_p16 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_s8 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_s16 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_s32 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_s64 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_u8 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_u16 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_u32 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsriq_n_u64 ^⚠	Experimental`neon,v7` Shift Right and Insert (immediate)
vsub_f32 ^⚠	Experimental`neon` and `v7` Subtract
vsub_s8 ^⚠	Experimental`neon` and `v7` Subtract
vsub_s16 ^⚠	Experimental`neon` and `v7` Subtract
vsub_s32 ^⚠	Experimental`neon` and `v7` Subtract
vsub_s64 ^⚠	Experimental`neon` and `v7` Subtract
vsub_u8 ^⚠	Experimental`neon` and `v7` Subtract
vsub_u16 ^⚠	Experimental`neon` and `v7` Subtract
vsub_u32 ^⚠	Experimental`neon` and `v7` Subtract
vsub_u64 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_f32 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_s8 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_s16 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_s32 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_s64 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_u8 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_u16 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_u32 ^⚠	Experimental`neon` and `v7` Subtract
vsubq_u64 ^⚠	Experimental`neon` and `v7` Subtract
vtbl1_p8 ^⚠	Experimental`neon,v7` Table look-up
vtbl1_s8 ^⚠	Experimental`neon,v7` Table look-up
vtbl1_u8 ^⚠	Experimental`neon,v7` Table look-up
vtbl2_p8 ^⚠	Experimental`neon,v7` Table look-up
vtbl2_s8 ^⚠	Experimental`neon,v7` Table look-up
vtbl2_u8 ^⚠	Experimental`neon,v7` Table look-up
vtbl3_p8 ^⚠	Experimental`neon,v7` Table look-up
vtbl3_s8 ^⚠	Experimental`neon,v7` Table look-up
vtbl3_u8 ^⚠	Experimental`neon,v7` Table look-up
vtbl4_p8 ^⚠	Experimental`neon,v7` Table look-up
vtbl4_s8 ^⚠	Experimental`neon,v7` Table look-up
vtbl4_u8 ^⚠	Experimental`neon,v7` Table look-up
vtbx1_p8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx1_s8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx1_u8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx2_p8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx2_s8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx2_u8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx3_p8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx3_s8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx3_u8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx4_p8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx4_s8 ^⚠	Experimental`neon,v7` Extended table look-up
vtbx4_u8 ^⚠	Experimental`neon,v7` Extended table look-up